- 1 - e08405-ps note on handling - gaas mmic?s are esd sensitive devices. s pecial handling precautions are required. sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illu strating the operation of the devices. sony cannot as sume responsibility for any problems aris ing out of the use of these circuits. CXM3517BER sp7t antenna switch module for gsm and umts or cdma dual mode handset description this switch is one of a range of low insertion loss, good linearity and high power mmic antenna switch modules for gsm/umts or cdma dual-mode handsets. the sony a.s.m. contains sp7t switch, a 1.8v cmos decoder and a dual-lpf on gsm transmit paths. the sony gaas junction gate phemt (jphemt) process is used for very low insertion loss and high linearity. the excellent insertion loss contributes to good sensitivity and longer talk time. * a.s.m. = antenna switch module (applications: quad band gsm and single band umts or cdma dual-mode handset) features ? low insertion loss: 0.80db (typ.) on tx1 (gsm low band tx) 0.80db (typ.) on tx2 (gsm high band tx) 0.33db (typ.) on trx (umts band i ) ? high attenuation: 30db (typ.) tx1 @ 2nd harmonic freq. 30db (typ.) tx2 @ 2nd harmonic freq. ? no dc blocking capacitors (small device footprint) small package: vqfn-22p (2.6mm 3.4mm 0.8mm typ.) ? low voltage operation: v dd = +2.65v ? cmos control line (ctla/ctlb/ctlc) ? rx paths are changeable for band assignment ? lead-free and rohs compliant structure gaas junction gate phemt (jphemt) switch, cmos decoder and dual-lpf
CXM3517BER - 2 - block diagram pin configuration ? built-in cmos decoder ant tx1 tx2 f2 f3 f10 f4 f5 f6 f14 f15 f9 f7 rx3 rx2 rx1 rx4 lpf1 lpf2 trx f1 19 20 21 22 11 10 9 8 15 14 13 12 18 17 16 4 5 6 7 23 24 1 2 3 tx2 gnd tx1 gnd gnd gnd ant gnd trx gnd rx4 rx3 rx2 rx1 ctla ctlb ctlc v dd vqfn-22p pkg (2.6mm 3.4mm 0.8mm typ.) gnd gnd gnd gnd top view 22 22 22 19 8 9 10 11 4 5 6 7 1 2 3 15 14 13 12 18 17 16 bottom view gnd gnd
CXM3517BER - 3 - pin description truth table *1 each rx path can be used from 869mhz to 1990mhz frequency, user can select these rx paths changeably. *2 state ?l? means a switch ?off?, state ?h? means a switch ?on?. pin no. symbol pin no. symbol 1gnd 13gnd 2 rx2 14 gnd 3 rx3 15 trx 4 rx4 16 gnd 5 rx1 17 ant 6gnd 18gnd 7gnd 19v dd 8 tx2 (gsm1800/1900) 20 ctlc 9 gnd 21 ctlb 10 gnd 22 ctla 11 tx1 (gsm850/900) 23 gnd (bottom) 12 gnd 24 gnd (bottom) state active path vctl state switch state *2 a b c f1f2f3f4f5f6f7f9f10f14f15 1tx1 h hl hllllll h hl h 2tx2 hlll hllllll hl h 3 rx1 *1 lllll hllll hl h h 4 rx2 *1 ll hlll hlll hl h h 5 rx3 *1 l h hllll hll hl h h 6 rx4 *1 l hllllll hl hl h h 7trx hl hllllll h h hll
CXM3517BER - 4 - electrical characteristics supply voltage value (ta = +25 c) logic value (ta = +25 c) absolute m aximum ratings *1 fr-4 (4 layers), 30mm sqr., t = 0.8mm item min. typ. max. unit bias voltage (v dd ) +2.5 +2.65 +3.3 v item state min. typ. max. unit control voltage (ctl-a/b/c) high +1.5 +1.8 +3.3 v low 0 ? +0.3 item ratings bias voltage (v dd ) 4.3v (ta: +25 c) control voltage (ctl-a/b/c) 4.3v (ta: +25 c) input power max. [tx1] *1 +36.5dbm (duty cycle: 25%) (ta: +25 c) input power max. [tx2] *1 +34.5dbm (duty cycle: 25%) (ta: +25 c) input power max. [trx] *1 +32dbm (ta: +25 c) input power max. [rx1, rx2, rx3, rx4] *1 +13dbm (ta: +25 c) operating temperature range ?30 to +90 c strage temperature range ?65 to +150 c
CXM3517BER - 5 - (v dd = 2.65v, vctl = 0/1.8v, ta: +25 c) item symbol path conditions min. typ. max. unit insertion loss i.l ant - tx1 *1 ? 0.80 1.00 db ant - tx2 *2 ? 0.80 1.00 ant - rx1, rx2, rx3, rx4 *3 ? 0.65 0.80 *4 ? 0.85 1.00 ant - trx *5 ? 0.33 0.50 *8 ? 0.25 0.40 isolation iso tx1 - rx1, rx2, rx3, rx4 *1 824 to 915mhz state 1 45 55 ? db tx1 - trx *1 824 to 915mhz state 1 30 40 ? tx1 - tx2 *1 824 to 915mhz state 1 18 21 ? tx1 - ant *1 880 to 915mhz state 3/4/5/6 22 26 ? *10 1710 to 1910mhz state 3/4/5/6 30 40 ? tx2 - ant *1 1760 to 1830mhz state 1 26 31 ? *1 2640 to 2745mhz state 1 26 31 ? *11 824 to 915mhz state 3/4/5/6 20 28 ? *2 1710 to 1910mhz state 3/4/5/6 19 23 ? tx2 - rx1, rx2, rx3, rx4 *2 1710 to 1910mhz state 2 40 50 ? tx2 - trx *2 1710 to 1910mhz state 2 25 30 ? tx2 - tx1 *2 1710 to 1910mhz state 2 28 31 ? trx - rx1, rx2, rx3, rx4 *5 1920 to 2170mhz state 7 40 50 ? *8 824 to 894mhz state 7 45 55 ? *9 1710 to 1990mhz state 7 45 55 ? trx - tx1 *5 1920 to 2170mhz state 7 30 39 ? *8 824 to 894mhz state 7 20 26 ? *9 1710 to 1990mhz state 7 30 39 ? trx - tx2 *5 1920 to 2170mhz state 7 20 24 ? *8 824 to 894mhz state 7 30 38 ? *9 1710 to 1990mhz state 7 20 25 ? v.s.w.r. vswr ant - tx1 824 to 915mhz ? 1.30 1.60 ? ant - tx2 1710 to 1910mhz ? 1.45 ant - rx1, rx2, rx3, rx4, trx 824 to 2170mhz ? 1.20 harmonic level 2fo tx1 - ant *1 ? ?48 ?36 dbm 3fo ? ?48 ?36 2fo tx2 - ant *2 ? ?52 ?36 3fo ? ?43 ?36 2fo trx - ant *5 ? ?54 ?36 3fo ? ?53 ?36 2fo trx - ant *8 ? ?60 ?36 3fo ? ?58 ?36
CXM3517BER - 6 - electrical characteristics are specified on s ony evb and with all rf ports terminated with 50 . *1 pin on tx1: +34dbm, 824 to 915mhz, v dd = 2.65v *2 pin on tx2: +32dbm, 1710 to 1910mhz, v dd = 2.65v *3 pin on ant: +10dbm, 869 to 960mhz, v dd = 2.65v *4 pin on ant: +10dbm, 1805 to 1990mhz, v dd = 2.65v *5 pin on trx: +26dbm, 1920 to 2170mhz, v dd = 2.65v *6 pin on trx: +20dbm, 1950mhz, pin on ant: ?15dbm, 190mhz, v dd = 2.65v *7 pin on trx: +20dbm, 1950mhz, pin on ant: ?15dbm, 1760mhz, v dd = 2.65v *8 pin on trx: +26dbm, 824 to 894mhz, v dd = 2.65v *9 pin on trx: +26dbm, 1710 to 1990mhz, v dd = 2.65v *10 pin on tx1: +5dbm, 1710 to 1910mhz, v dd = 2.65v *11 pin on tx2: +5dbm, 824 to 915mhz, v dd = 2.65v *12 measured with recommended circuit inter modulation distortion imd2 trx - ant *6 , *12 ? ?107 ?105 dbm imd3 trx - ant *7 , *12 ? ?106 ?102 attenuation att tx1 - ant 1648 to 1830mhz 25 30 ? db 2472 to 2745mhz 25 41 ? 3296 to 3660mhz 20 26 ? tx2 - ant 3420 to 3820mhz 25 30 ? 5130 to 5730mhz 25 33 ? switching time ts 90% off ? 90% on ? 3 5 s control current ictl v dd = 2.65v, vctl = 1.8v ? 5 20 a supply current idd active mode ? 0.18 0.40 ma item symbol path conditions min. typ. max. unit
CXM3517BER - 7 - recommended circuit note) 1. no dc blocking capacitors are required on all rf ports. 2. dc levels of all rf ports are gnd. 3. l1 (22nh) and c1 (22pf) are recomm ended on ant port for esd protection. 6 4 5 8 3 1 2 9 10 11 13 15 14 16 18 17 22 21 20 19 vqfn-22p pkg (2.6mm 3.4mm 0.8mm typ.) top view 7 12 c1 l1 c2 100pf ant trx gnd gnd gnd gnd gnd rx2 rx1 rx4 rx3 gnd gnd gnd tx2 tx1 gnd gnd ctla ctlc ctlb v dd 23 gnd gnd 24
CXM3517BER - 8 - pin 1 index pcb layout template 3.4 2.6 (0.95) (0.55) ( 0.5) [detailed view a] a 2.6 3.0 ? pkg size: 3.4mm 2.6mm ? pin pitch: 0.4mm : land : mask (open area) : resist (open area) ? metal mask thickness: 110m 0.4 0.62 0.72 0.89 0.42 0.52 r0.2 3.4 (pkg line) 3.8 r0.2 r0.2 r0.2 1.2 1.4 1.5 0.4 0.1 0.21 0.15 0.26 ? mask corner r = 0.05mm 0.2 0.3 0.3 0.5 0.05 r0.05 c0.1 pkg line 0.25 0.79
CXM3517BER - 9 - recommended pcb design 0.09 0.80 2.31 0.58 1.00 1.45 (unit: mm) gnd via hole for lpf (light blue) pcb metal pattern ic (vqfn-22p package) gnd via hole for switch 1pin the positions of these via holes are recommended for stable attenuation. independent gnd with via hole 0.55 0.25
CXM3517BER - 10 - sony corporation package outline (unit: mm) lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec.
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